VDP2 VRAM cycle pattern CPU R/W access timings

mrkotfw

Mid Boss
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What is the implication here? An auxiliary work RAM? How can VRAM act as a framebuffer when dealing with cell scroll screens? Does this imply that parts of the display can be read back into memory?

Basic question. If CPU R/W access is selected, when is it okay to access VRAM? Is it that the reads and writes can happen at any time, but are buffered/queued in some fashion?
 
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