HOWTO 2cpu

[ob1]

Concerning the 2 SH2, I am a newbie (I wish it was the only thing ).

So, we got 2 CPU, and one of them is defined as "slave". I guess it is called so, because the master tell him what to do.


How does it run ?

1rst possibility : the DSP way.

The master and the slave both have a start address, defined somewhere very early. It says that the master starts at let's say 0x60000000 and the slave starts at, ... 0x60004000. When the master wants the slave to do something, it writes some real code at 0x60004000 ... et voilà. The slave has its very own code, and it keeps running it.


2nd possibility : the 2 CPU way.

This is the way I'd like the SH2s to run, but I guess it would be done by an OS. The CPUs have a bunch of job to be done. The first one that is ready takes the head of the jobs and runs it. Meanwhile, the second CPU takes the next job, and so on ... But I guess this way is not implementing.


3rd possibility : can not figure yet.


Has someone already played with 2 CPU's ?

How do they run ?

Isn't my DSP way a little bit simple-minded ?

 

[RockinB]

On startup, only the master CPU runs, the slave has to be started manually. The CPU program position in memory is defined by the IP.BIN for both, master and slave.

Basically (all dual CPU samples of SBL, the SGL and my SGL replacement work similar) there is a small loop running on slave which is waiting for requests by the master.

Requests can be communicated using the FRT (Free Running Timer) or (the slower, memory traffic causing way) by cache-through reading a certain memory position (has been done in earlier SGL versions).

In SGL there is a function called slSlaveFunc(), with which you just submit a function to the slave joblist. Very easy to use.

However, balancing the load evenly across master and slave is a difficult (yet not completely solved) task. In SGL, the slPutPolygon function decides depending on the slave cpu state, which parts are to be done on which cpu (well, not that much flexible like it sounds here).

There is also the time when waiting for the VBLANK, where master and slave a idle. A Method in SGL is to use slPutPolygonS, which is only executed on slave. This way, the slave is kept busy while master waits fir vblank.

I have used dual CPUs via slSlaveFunc() in various emulators, in a voxel rendering engine and in my texture mapping/resampling stuff. The main problem is to ensure that the data used by master and slave is distinct and if both read and write the same variables, then only in a manner wanted by the coder.

 

[ob1]

Ok, just summed it up : IP.BIN gives STACK-M and STACK-S, and the SEGA's 2 CPU guide shows how to communicate.

Got it.

DSP way is easy, balancing load is all the hard.


Thank you.

 

[ob1]

Well .. I have read a lot of docs, disc specification as well, and I don't understand some things very well.

The IP.BIN tells the stack for both CPU, right. But that's just the stack, not the program counter (PC). Later, with the SH linkage command, I got SYSSTART set to the 1rst read address. I guess that SYSStart set the Master PC, but what about the slave ? How to set PC for each CPU ?


More. The master stack area is by default from 06001000h to 06001FFFh, while the slave is from 06000000h to 06000FFFh. I assume that memory between 06000000h and 06002000h is RAM, and not cache. But, where does the slave CPU private Work RAM lay ? And how do I tell the slave CPU to run in 4kB cache mode or 2kB cache/2kB RAM mode ? Does the Master CPU have access to the slave private Work RAM ?


Quote me if I'm wrong, but we don't have access to what's inside cache ?


You see, I've been messing around docs the whole day long. I've learned some things, but got a lot more to know !!!

 

[antime]

When booting from CD, the slave CPU is halted and the master CPU starts executing from the AIP (application initial program). After that everything is up to you, the programmer. The "Disc Format Standards Specification Sheet" document describes the boot process in more detail.

For information regarding the CPU caches, see the SH7064 manual.

 

[mrkotfw]

0x06000000-0x07ffffff : High Work RAM

0x06000000-0x060001ff : SH-2 master vector table

0x06000200-0x06000bff : BIOS functions

0x06000c00-0x06000fff : BIOS seems to copy small area of the "IP.BIN"

0x06001000-0x06003fff : ???

0x06004000-           : Program

I may be wrong...

 

[ob1]

For information regarding the CPU caches, see the SH7064 manual.

Oh great !!! I figured that my SuperH and Renesas docs would be enough, but your 7604 docs is much more complete concerning cache. Great ressource, once more. Thank you. I know what I'm gonna read this week-end !!!


I'll increase my skill on booting by the way

 

[ob1]

Here it is.

At boot, the Boot ROM states the slave CPU VBR (the PC in the mean time) is at 0600 0400h. The Boot ROM also settles the slave CPU SP to 0600 1000h. Then, the IP.BIN file defines the Slave CPU Stack Area, 0600 0D00h to 0600 1000h by default.

I guess that writing to 0600 0400h would tell the Slave CPU where to start.

The IP.BIN also defines the Master CPU Stack area (0600 1000h to 0600 2000h) by default and the 1rst read address, the place where the first file is going to be copied. I don't know yet if it is in the mean time, or later, in the AIP, that the Master CPU PC is set to this address, 0600 4000h for example.


To turn the Slave CPU on, you've got to use the SMPC. In the Command Register (COMREG, at 2010 001Fh cache-through), write the command 02h (byte or word ?). You know the Slave CPU is turned on when the register OREG31 (2010 005Fh cache-trhough) switches from 03h to 02h.


Cache configuration, direct cache access and private RAM access is done using private address. For each CPU, the Cache Control Register defines the cache status. The CCR register lays at FFFF FFE92h. The 3rd bit (TW) of this register defines the cache mode : 0 = 4kB cache ; 1 = 2kB cache / 2kB RAM.

The private Work RAM of each CPU is from C000 0000h to C000 0800h. Obviously, the private Work RAM of one CPU is not available to the other.


Each CPU run the code from its initial PC.


Terminology

VBR : Vector Base Register

SP : Stack Pointer

PC : Program Counter


Sources :

Dual CPU User's guide §4.4 Initialization by the Boot ROM

Disc format standards specification §4.0 Boot System

SMPC User's manual

Hitach SH7604 Hardware Manual §8 Cache





By the way, I have started a kind of SEGA Saturn Programming FAQ.

 

[ob1]

	MOV	#1,R2

	MOV.L	SF,R1

waitSMPC:

	MOV.B	@R1,R0

	CMP/EQ	#1,R0

	BT	waitSMPC

	NOP

	MOV.B	R2,@r1

	MOV.L	COMREG,R1

	MOV	#2,R2

	MOV.B	R2,@R1

	MOV.L	OREG31,R1

waitSSHON:

	MOV.B	@R1,R0

	CMP/EQ	#3,R0

	BT	waitSSHON

	NOP

SF:

	dc.l	$20100063

COMREG:

	dc.l	$2010001F

OREG31:

	dc.l	$2010005F

Inspired by Piratero : http://forums.segaxtreme.net/showpost.php?p=152039&postcount=4

 

[antime]

I guess that writing to 0600 0400h would tell the Slave CPU where to start.

When the slave CPU starts, the default BIOS functionality will jump to the address stored in 0x6000250.

(Edit: If you look at the example in the dual CPU user's guide the slave entry point is set using SYS_SETSINT to change vector 0x94. The default master VBR points to 0x6000000 and 0x94 * 4 == 0x250.)

I don't know yet if it is in the mean time, or later, in the AIP, that the Master CPU PC is set to this address, 0600 4000h for example.

It is completely up to the AIP what to do after the first read file has been loaded.

 

[ob1]

	MOV	#1,R2

	... turn the Slave CPU ON[/quote]


... did I really write this one year ago ?!?

 

[dibz]

Yeah, yeah you did. Nice to see some new ~old~ members.