The PRINA & PRINB Regs probably aren't needed for one background. The timing regs are simple use the VDP2 manual as a reference. In your demo the VRAM is partitioned into 4 banks A0, A1, B0, & B1 by bits 8-9 in RAMCTL so we set CYCA0, CYCA1, CYCB0 & CYCB1. If we only partitioned the VRAM into A...