Hi together,
I'm currently trying to wrap my head around how to design a simple flash (rom only - at least for now) card.
I think I've got a grasp of the basics, thanks to the awesome designs & documentation on this forum and otherwise (from antime, Chilly Willy, ExCyber, cafe-alpha and Rockin'-B to name a few). It would be great if you could have a look and confirm my understanding so I'm not making too many rookie mistakes 🙂
Basically for a simple flash rom-only card the following signals on the A-Bus are needed:
Adresslines AA00-AAXX (depending on the flash rom size)
Datalines D0-D15 (so the SCU is reading & writing words natively)
Control signals: ACS0, ARD, AWR0 all ACTIVE LOW
Timing:
Basically I'd expect a read request from the SCU to the card rom to look like this - ACS0, ARD go low while AWR0 stays high.
After this the data (D0-D15) corresponding to the request adress (AA00-AAXX) is expected to be pushed/driven on the bus by the card after X cycle waitstates.
The amount of waitstates can be changed (up to 15 cycles) but requires setting a register = at least a bit of flash has to be able to respond with the default (=0) waitstate access speed. This translates to < 50 ns required response times initially, which could be extended to ~ 750 ns later.
Writing: Similar story but AWR0 is low and ARD high.
It would be great if anybody could confirm if my basic understanding is correct or not. I'm especially interested in the access timing requirements so I might be able to explore the use of different flash ICs with a microcontroller-driven interface or similar....
Thanks in advance !
I'm currently trying to wrap my head around how to design a simple flash (rom only - at least for now) card.
I think I've got a grasp of the basics, thanks to the awesome designs & documentation on this forum and otherwise (from antime, Chilly Willy, ExCyber, cafe-alpha and Rockin'-B to name a few). It would be great if you could have a look and confirm my understanding so I'm not making too many rookie mistakes 🙂
Basically for a simple flash rom-only card the following signals on the A-Bus are needed:
Adresslines AA00-AAXX (depending on the flash rom size)
Datalines D0-D15 (so the SCU is reading & writing words natively)
Control signals: ACS0, ARD, AWR0 all ACTIVE LOW
Timing:
Basically I'd expect a read request from the SCU to the card rom to look like this - ACS0, ARD go low while AWR0 stays high.
After this the data (D0-D15) corresponding to the request adress (AA00-AAXX) is expected to be pushed/driven on the bus by the card after X cycle waitstates.
The amount of waitstates can be changed (up to 15 cycles) but requires setting a register = at least a bit of flash has to be able to respond with the default (=0) waitstate access speed. This translates to < 50 ns required response times initially, which could be extended to ~ 750 ns later.
Writing: Similar story but AWR0 is low and ARD high.
It would be great if anybody could confirm if my basic understanding is correct or not. I'm especially interested in the access timing requirements so I might be able to explore the use of different flash ICs with a microcontroller-driven interface or similar....
Thanks in advance !
