After discussing cycle pattern registers with VBT, I was wondering about the undocumented bits listed in the VDP2 manual, which are covered over when the page renders:
$18000C - (Labeled as "RESERVED")
Bit 8 (VRAMCE)
0= No change function, VRAM-A and VRAM-B are display RAM
1= Change function, either VRAM-A or VRAM-B as display RAM
Bit 0 (VRAMSL)
0= Use VRAM-A for CPU RAM
1= Use VRAM-B for CPU RAM
I can't find the webpage that had schematics for the Saturn, but assuming the VRAMs are two separate chips (A,B), it sounds like you can 'disconnect' one from the display refresh logic and give the CPU unlimited access to it without the VDP2 have priority when it comes to sharing cycles.
Has anyone tried this and checked what kind of performance gains you can get?
I'm also interested in what happens if you set as many cycle pattern registers as possible to $EEEE (depending on the bank allocation) and try SCU DMA. I think "CPU access" refers to any of SH-2 DMA, SCU DMA, or SH-2 reads/writes. How closely does that speed match VRAM access time during V-Blank?
$18000C - (Labeled as "RESERVED")
Bit 8 (VRAMCE)
0= No change function, VRAM-A and VRAM-B are display RAM
1= Change function, either VRAM-A or VRAM-B as display RAM
Bit 0 (VRAMSL)
0= Use VRAM-A for CPU RAM
1= Use VRAM-B for CPU RAM
I can't find the webpage that had schematics for the Saturn, but assuming the VRAMs are two separate chips (A,B), it sounds like you can 'disconnect' one from the display refresh logic and give the CPU unlimited access to it without the VDP2 have priority when it comes to sharing cycles.
Has anyone tried this and checked what kind of performance gains you can get?
I'm also interested in what happens if you set as many cycle pattern registers as possible to $EEEE (depending on the bank allocation) and try SCU DMA. I think "CPU access" refers to any of SH-2 DMA, SCU DMA, or SH-2 reads/writes. How closely does that speed match VRAM access time during V-Blank?