I'm trying to map a NVRAM chip within the $800000-$9FFFFF memory range, and don't want to use $000000-$7FFFFF or the other areas where /DTACK is managed by the hardware. So I'll need to assert it myself, but that's where things get confusing. I've been looking at other 68000 designs to see how this is done.
In one circuit I've seen, the CPU clock is used to clock a hex latch that has each output feeding into the next input (Q0->D1, Q1->D2, etc.). The first input is pulled low when a range of memory is enabled (in this case an EPROM) and R//W goes high. So the read access sets the timer (conceptually a shift register) in motion.
This way a '0' bit is shifted through the latch per clock cycle, and the output of each stage goes low after a specific unit of time such as 125ns, 250ns, 375ns, etc. Whichever output corresponds to the desired delay is fed to /DTACK. It makes sense but needs a few TTL chips to implement, I can't spare a lot of PCB space.
A simpler example has a flip-flop that latches /AS and outputs it to /DTACK, clocked by the CPU clock. Though I'm not clear if these means /DTACK follows /AS or is delayed by one cycle of the master clock (which would be 130ns for the Genesis, a reasonable delay). But this circuit also used the preset input of the flip-flop to delay /DTACK assertion by some host devices which seem to always be enabled so it's hard to tell how much time really passes.
Any ideas about easy ways to handle this?
Going by the NVRAM datasheet, there are delays between the time that /CS and /RD are asserted and it drives the bus during a read (isn't this called setup time?), and a similar delay from the time /CS and /WR are asserted and the moment when it actually latches the data bus.
So the /DTACK delay has to meet or exceed these two timing requirements, right?
In one circuit I've seen, the CPU clock is used to clock a hex latch that has each output feeding into the next input (Q0->D1, Q1->D2, etc.). The first input is pulled low when a range of memory is enabled (in this case an EPROM) and R//W goes high. So the read access sets the timer (conceptually a shift register) in motion.
This way a '0' bit is shifted through the latch per clock cycle, and the output of each stage goes low after a specific unit of time such as 125ns, 250ns, 375ns, etc. Whichever output corresponds to the desired delay is fed to /DTACK. It makes sense but needs a few TTL chips to implement, I can't spare a lot of PCB space.
A simpler example has a flip-flop that latches /AS and outputs it to /DTACK, clocked by the CPU clock. Though I'm not clear if these means /DTACK follows /AS or is delayed by one cycle of the master clock (which would be 130ns for the Genesis, a reasonable delay). But this circuit also used the preset input of the flip-flop to delay /DTACK assertion by some host devices which seem to always be enabled so it's hard to tell how much time really passes.
Any ideas about easy ways to handle this?
Going by the NVRAM datasheet, there are delays between the time that /CS and /RD are asserted and it drives the bus during a read (isn't this called setup time?), and a similar delay from the time /CS and /WR are asserted and the moment when it actually latches the data bus.
So the /DTACK delay has to meet or exceed these two timing requirements, right?