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Genesis signal analysis

Discussion in 'Genesis - SCD - 32X Dev' started by cgfm2, May 14, 2006.

  1. cgfm2

    cgfm2 New Member

    I was probing around the Genesis and checked out some of the signals (all while /CART is grounded). Address ranges that make the system lock up (no DTACK) weren't included.

    Cartridge port:

    /ASEL is asserted for reads and writes within 000000-7FFFFF

    /CAS_2 is asserted for reads and writes within 000000-7FFFFF

    /CE_0 is asserted for reads and writes within 000000-3FFFFF

    /CAS_0 is asserted for reads *only* within 000000-7FFFFF

    /TIME is asserted for reads and writes within A13000-A130FF

    Timing-wise, pulses on /CAS_0, /CE_0, /AS are identical, pulses on /ASEL and /DTACK are identical but longer, /CAS_2 was the longest.

    Other signals (68K work RAM):

    /RAS_2 is asserted for reads and writes within E00000-FFFFFF

    The schematics show /RAS_2 on the expansion connector; I haven't tested it but a multimeter check on the console I was using showed that /RAS_2 on the expansion port was not related to the work RAM /CS pins, which are connected to '/RAS_2' in the schematic.

    Expansion port:

    /FDWR is asserted for writes only within A12000-A120FF

    /DISK is asserted for reads and writes within A12000-A120FF

    /FDC is asserted for reads and writes within A12000-A120FF

    /ROM is asserted for reads and writes within 400000-5FFFFF

    Not sure what's with all the duplication of the floppy disk related signals. I don't know which one(s) the Sega CD uses to map it's registers to the $A120xx range.

    Probably /ROM changes to 000000-1FFFFF (or 3FFFFF as the high range?) when /CART is high for use by the Sega CD's BIOS ROM.

    When A11200=$0100 (DRAM enabled), there is an extra pulse on /CE_0 about every 200 EDCLKs. This same pulse also appears on /CAS_2 regardless of A11200, both occur at the same time.

    Likewise, about every 222 EDCLKs there is something like a /DTACK delay where all signals (/CAS_0, /CE_0, /DTACK, /ASEL, /CAS_2) are stretched out for 2 or 3 68000 clocks. This occurs when running out of ROM or RAM. I checked /BR to see if the VDP was taking over the bus for DMA, but it isn't. Not sure what that's all about.
     
  2. patroclus02

    patroclus02 New Member

    Hi,

    I’m doing some tests while cart high, booting code from expansion port. And there’re some differences.

    I thought /ROM was a $000000-$03FFFF strobe, but it isn’t. It is a $000000-$1FFFFF strobe.

    /ASEL pulses are shorter than /ROM’s

    /CAS_2 and /FDWR are even shorters.

    Also, /CAS_2 is not the longest pulse anymore.

    /CAS_0 asserts for readings.

    /DISK seems to be asserted for reads and writes within A12000-A120FF, *but*

    /FDWR asserts everytime you access $000000-$3FFFFF. It does not for RAM accesses (neither reads or writes). Pulses are 150ns, same as CAS_2.

    you can see details in the first timing diagram attached.

    /OE is CAS_0.

    The first /LWR pulse is a low byte write to $040001.

    The next /LWR pulse is a low byte write to $200001.

    You can see here that /ROM asserts for addresses above $03FFFF and below $200000.

    Thus, it must be a $000000-$1FFFFF strobe.

    -----------------------

    The next timing diagram shows /CAS_2

    /ROM pulses are 330ns wide.

    /ASEL pulses are 220ns wide.

    /CAS2 pulses are 150ns wide.

    You can see larger pulses at the begining. (600, 500 and 420 ns respectivily).

    As /CAS_0 (/OE) asserts for 330ns, memory acces time must be 330 ns or lower for it to work on Genesis. This is quite low speed. SNES demands 200ns or even 120ns access time ROMs.

    *But* /LWR and /UWR strobes assert for 200ns, so *probably*, memory acces time has to be 200ns or faster, as SNES ?
     

    Attached Files:

  3. Pinchy

    Pinchy New Member

    Isnt that from the intronix logic analyzer?


    How do you like that thing so far?


    How many seconds can you record using just those channels like in the snapshots?
     
  4. ExCyber

    ExCyber Staff Member

    The only thing that immediately comes to mind is a delay for DRAM refresh, but then I'm biased. ;)

     
  5. patroclus02

    patroclus02 New Member

    Sorry to take so much to answer, but I had some problems, and had to leave my projects a side for a while.

    I love it. This logic analyzer is great. The only drawback is 2048k samples per channel. But has lots of features and works great.

    Please, if you have any question, ask me.
     

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