Ponut
Gear Supporter
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Processors:
"2x Hitachi SH-2 running @ <given MHz>"
Technically incorrect; should be:
"2x Hitachi SH-7604 CPUs running at <NTSC Freq> in NTSC regions, <PAL freq> in PAL regions
This section should clarify that the SH-7604 is a semicustom chip with the SH-2 ISA.
"up to 4/instructions per cycle" - is that true? It is at most two, right?
"4x internal fixed point math processors" - what? and it calls the MULT unit a DSP?
This section should mention the division unit as unique to the SH-7604.
Do we need to specify the bit depth of the division unit? 64bit / 32 bit
The explicit bus (the "C" or "CPU-Bus") should be noted as the location of these CPUs
The addressable memory of the CPUs should be noted and memory assigned to C bus
"SCU"
The frequency of the SCU should be mentioned here
The SCU-DSP should be mentioned as a logical processor with limited program size,
not a "geometry processor". Saying it has 85 MIPS is a misrepresentation.
"Center of all RAM Bus" should be mentioned as the location of the SCU
The addressable memory of the SCU should be noted
"CDB"
The SH-1 should be noted as inaccessable for programming
It should be noted that the CDB is on the "A bus"
The addressable memory of the CDB should be noted
(transfers available to-from rest of system, but generally SH-1 can address an assigned 512kb)
"SMPC"
The SMPC should be as noted on the "C" bus
Why give a MIPS value for this?
"SCSP" - is YMF292 correct?
It should be noted that the SCSP-DSP is *not* a logical processor (still useful)
It should be noted about the addressable memory of this unit (512kb)
It should be noted that this is located on the "B" Bus
"Sound CPU" -
should be noted that its addressable location and bandwidth is shared with SCSP
"VDP1" - In all cases both NTSC and PAL frequencies need to be noted.
But here especially we want to highlight that the x224 and x240 modes change frequency.
Where are they getting that bus width from? Does it matter?
Word length?
The bullet point here shouldn't be that.
It should be that VDP1 draws to a framebuffer that VDP2 encodes into the video output.
It should be noted that pixels can be 16-bit in low-res modes or 8-bit in high res modes.
It should be noted that VDP1 accepts all commands in a fixed 32-byte size.
It should be noted that pixels can be either indexed color or direct RGB.
It should be noted that VDP1 can do color calculation.
VDP1 is on the B-bus with an addressable 512kb of RAM for itself. (in addition to framebuffers)
"VDP2" - It particularly must be noted that VDP2 contains the video DAC.
It is ultimately responsible for how anything the system is doing looks on-screen.
VDP2 is on the B-bus with a segmented sequential total of 512kb of addressable RAM for itself.
Pipeline:
Again, the main CPUs do not qualify as DSP. The SCU-DSP does.
I would rather not that geometry processing can be done on any logical processor in the system,
but is typically only done on one or two main CPUs.
*Now* they're noting the PAL/NTSC difference?
Refresh rate: the 30hz mode is interlaced video. That's... still 60. (same for 25/50)
"RGBA"? I know there's extended color calculation, but...
I don't recall a 32-bit pixel format like that.
I *do* know there's a 24-bit mode (whose pixels are 4-bytes anyway).
Someone clarify?
The rest of this is too much, lol
am I actually going to write the final changes? nah, just making notes because apparently you can edit it now
Processors:
"2x Hitachi SH-2 running @ <given MHz>"
Technically incorrect; should be:
"2x Hitachi SH-7604 CPUs running at <NTSC Freq> in NTSC regions, <PAL freq> in PAL regions
This section should clarify that the SH-7604 is a semicustom chip with the SH-2 ISA.
"up to 4/instructions per cycle" - is that true? It is at most two, right?
"4x internal fixed point math processors" - what? and it calls the MULT unit a DSP?
This section should mention the division unit as unique to the SH-7604.
Do we need to specify the bit depth of the division unit? 64bit / 32 bit
The explicit bus (the "C" or "CPU-Bus") should be noted as the location of these CPUs
The addressable memory of the CPUs should be noted and memory assigned to C bus
"SCU"
The frequency of the SCU should be mentioned here
The SCU-DSP should be mentioned as a logical processor with limited program size,
not a "geometry processor". Saying it has 85 MIPS is a misrepresentation.
"Center of all RAM Bus" should be mentioned as the location of the SCU
The addressable memory of the SCU should be noted
"CDB"
The SH-1 should be noted as inaccessable for programming
It should be noted that the CDB is on the "A bus"
The addressable memory of the CDB should be noted
(transfers available to-from rest of system, but generally SH-1 can address an assigned 512kb)
"SMPC"
The SMPC should be as noted on the "C" bus
Why give a MIPS value for this?
"SCSP" - is YMF292 correct?
It should be noted that the SCSP-DSP is *not* a logical processor (still useful)
It should be noted about the addressable memory of this unit (512kb)
It should be noted that this is located on the "B" Bus
"Sound CPU" -
should be noted that its addressable location and bandwidth is shared with SCSP
"VDP1" - In all cases both NTSC and PAL frequencies need to be noted.
But here especially we want to highlight that the x224 and x240 modes change frequency.
Where are they getting that bus width from? Does it matter?
Word length?
The bullet point here shouldn't be that.
It should be that VDP1 draws to a framebuffer that VDP2 encodes into the video output.
It should be noted that pixels can be 16-bit in low-res modes or 8-bit in high res modes.
It should be noted that VDP1 accepts all commands in a fixed 32-byte size.
It should be noted that pixels can be either indexed color or direct RGB.
It should be noted that VDP1 can do color calculation.
VDP1 is on the B-bus with an addressable 512kb of RAM for itself. (in addition to framebuffers)
"VDP2" - It particularly must be noted that VDP2 contains the video DAC.
It is ultimately responsible for how anything the system is doing looks on-screen.
VDP2 is on the B-bus with a segmented sequential total of 512kb of addressable RAM for itself.
Pipeline:
Again, the main CPUs do not qualify as DSP. The SCU-DSP does.
I would rather not that geometry processing can be done on any logical processor in the system,
but is typically only done on one or two main CPUs.
*Now* they're noting the PAL/NTSC difference?
Refresh rate: the 30hz mode is interlaced video. That's... still 60. (same for 25/50)
"RGBA"? I know there's extended color calculation, but...
I don't recall a 32-bit pixel format like that.
I *do* know there's a 24-bit mode (whose pixels are 4-bytes anyway).
Someone clarify?
The rest of this is too much, lol
am I actually going to write the final changes? nah, just making notes because apparently you can edit it now
