mrkotfw
Mid Boss
i'm having some problems in getting tiles displayed, it could be yabause not supporting a few things but i'd also like to know what i'm doing wrong.
well, here's what the code below does: it displays a 256 color 16x16 made up of 8x8 tiles. i think the problem is telling the saturn where the tiles and map data is stored.
the macros below may be wrong (can't blame me, the names are difficult to remember)
well, here's what the code below does: it displays a 256 color 16x16 made up of 8x8 tiles. i think the problem is telling the saturn where the tiles and map data is stored.
Code:
#include <color.h>
#define NBG0_CEL_ADR (VDP2_VRAM_A0)
#define NBG0_MAP_ADR (VDP2_VRAM_A0 + 0x1000)
#define NBG0_COL_ADR (VDP2_COLRAM)
int
main(void)
{
int j = 0;
clear_vdp();
TVMD = HRESO0 | VRESO0 | BDCLMD;
BGON = N1ON;
CHCTLA = N1CHCN0;
RAMCTL = VRAMD | VRBMD;
MPABN1 = N1MPA0 | N1MPB0;
MPCDN1 = N1MPA0 | N1MPB0;
back_screen((void *)BACK_CRAM,RGB(28,20,16));
vram(nbg0_gfx,(u8 *)NBG0_CEL_ADR,SIZE(nbg0_gfx));
pram(nbg0_pal,(u16 *)NBG0_COL_ADR,SIZE(nbg0_pal));
TVMD |= DISP;
for(;;)
{
while((TVSTAT & 8) == 0);
*(u16 *)(NBG0_MAP_ADR + j) = 0x0;
*(u16 *)(NBG0_MAP_ADR + (j + 1)) = 0x2;
j++;
while((TVSTAT & 8) != 0);
}
return 0;
}
void
clear_vdp(void)
{
int j;
u16 *vdp2_io = (u16 *)(VDP2_VRAM_A0 + 0x180000);
for(j = 0; j < 0xFF; j++)
{
vdp2_io[j] = 0x0;
}
}
void
back_screen(void *adr, u32 col)
{
u32 *vram_s = (u32 *)adr;
BKTAU = (((*vram_s >> 17) & 0x7) | (col & 0x8000));
BKTAL = ((*vram_s >> 1) & 0xFFFF);
*(u32 *)vram_s = (col & ~0x8000);
}
void
vram(const u8 *dat, void *adr, u32 len)
{
int j;
u8 *vram_s = (u8 *)adr;
for(j = 0; j < len; j++) {
*vram_s++ = *dat++;
}
}
void
pram(const u16 *dat, void *adr, u32 len)
{
int j;
u16 *pram_s = (u16 *)adr;
for(j = 0; j < len; j++) {
*pram_s++ = *dat++;
}
}
the macros below may be wrong (can't blame me, the names are difficult to remember)

Code:
#ifndef __CORE_H__
#define __CORE_H__
#include <type.h>
#define VDP2_VRAM_A0 0x25E00000
#define VDP2_VRAM_A1 0x25E20000
#define VDP2_VRAM_B0 0x25E40000
#define VDP2_VRAM_B1 0x25E60000
#define NBG0_MAP (CGN01_RAM + 0x16000)
#define NBG1_MAP (CGN01_RAM + 0x18000)
#define KTBL0_RAM VDP2_VRAM_A1
#define BACK_CRAM (KTBL0_RAM + 0x1FFFE)
#define VDP2_COLRAM 0x25F00000
#define TVMD *(vu16 *)(VDP2_VRAM_A0 + 0x180000)
#define EXTEN *(vu16 *)(VDP2_VRAM_A0 + 0x180002)
#define TVSTAT *(vu16 *)(VDP2_VRAM_A0 + 0x180004)
#define VRSIZE *(vu16 *)(VDP2_VRAM_A0 + 0x180006)
#define RAMCTL *(vu16 *)(VDP2_VRAM_A0 + 0x18000E)
#define BGON *(vu16 *)(VDP2_VRAM_A0 + 0x180020)
#define CHCTLA *(vu16 *)(VDP2_VRAM_A0 + 0x180028)
#define CHCTLB *(vu16 *)(VDP2_VRAM_A0 + 0x18002A)
#define BKTAU *(vu32 *)(VDP2_VRAM_A0 + 0x1800AC)
#define BKTAL *(vu32 *)(VDP2_VRAM_A0 + 0x1800AE)
#define LCTAL *(vu16 *)(VDP2_VRAM_A0 + 0x1800AA)
#define LCTAU *(vu16 *)(VDP2_VRAM_A0 + 0x1800AC)
#define PNCN0 *(vu16 *)(VDP2_VRAM_A0 + 0x180030)
#define PNCN1 *(vu16 *)(VDP2_VRAM_A0 + 0x180032)
#define PNCN2 *(vu16 *)(VDP2_VRAM_A0 + 0x180034)
#define PNCN3 *(vu16 *)(VDP2_VRAM_A0 + 0x180036)
#define PLSZ *(vu16 *)(VDP2_VRAM_A0 + 0x18003A)
#define MPABN0 *(vu16 *)(VDP2_VRAM_A0 + 0x180040)
#define MPCDN0 *(vu16 *)(VDP2_VRAM_A0 + 0x180042)
#define MPABN1 *(vu16 *)(VDP2_VRAM_A0 + 0x180044)
#define MPCDN1 *(vu16 *)(VDP2_VRAM_A0 + 0x180046)
#define DISP (1 << 15)
#define BDCLMD (1 << 8)
#define LSMD1 (1 << 7)
#define LSMD0 (1 << 6)
#define VRESO1 (1 << 5)
#define VRESO0 (1 << 4)
#define HRESO2 (1 << 2)
#define HRESO1 (1 << 1)
#define HRESO0 (1 << 0)
#define EXLTEN (1 << 9)
#define EXSYEN (1 << 8)
#define DASEL (1 << 1)
#define EXBGEN (1 << 0)
#define EXLTFG (1 << 9)
#define EXSYFG (1 << 8)
#define VBLANK (1 << 3)
#define HBLANK (1 << 2)
#define ODD (1 << 1)
#define PAL (1 << 0)
#define VRAMSZ (1 << 15)
#define R0TPON (1 << 12)
#define N3TPON (1 << 11)
#define N2TPON (1 << 10)
#define N1TPON (1 << 9)
#define N0TPON (1 << 8)
#define R1ON (1 << 5)
#define R0ON (1 << 4)
#define N3ON (1 << 3)
#define N2ON (1 << 2)
#define N1ON (1 << 1)
#define N0ON (1 << 0)
#define N0CHCN0 (1 << 4)
#define N0CHCN1 (1 << 5)
#define N0CHCN2 (1 << 6)
#define N0BMSZ0 (1 << 2)
#define N0CHSZ (1 << 0)
#define N1CHCN0 (1 << 12)
#define N1CHCN1 (1 << 13)
#define BKCLMD (1 << 15)
#define N0PNB (1 << 15)
#define N0CNSM (1 << 14)
#define N1PNB (1 << 15)
#define N1CNSM (1 << 14)
#define N0BMEN (1 << 1)
#define N1BMEN (1 << 9)
#define VRBMD (1 << 9)
#define VRAMD (1 << 9)
#define N0MPB0 (1 << 8)
#define N0MPA0 (1 << 0)
#define N1MPA0 (1 << 8)
#define N1MPB0 (1 << 0)
#ifndef NULL
#define NULL (void *)0
#endif
#define RGB(r,g,b) ((r) | ((g) << 5) | ((b) << 10))
#define SIZE(size) (sizeof(size) / sizeof(size[0]))
#endif