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I couldnt find his vdp verilog, that might be private. Maybe someone with access to his paetron would know if hes instrumenting the hardware or just basing his HW design on the existing docs/emulator logic
You could make an in-circuit emulator or jtag interface by modifying the SH-2 core, and yeah you could add whatever op codes you want since you are defining the processor. Just think of it as a modifyable saturn hw clone. The limiting factor will be space since the de10 nano uses a smaller fpga, and excess hw will affect routing. His SH2 src is here, missed it the other day. GitHub - srg320/SH