There is an undocumented restriction on VDP2 VRAM cycle patterns:
(correct me if I'm wrong)
If some data spans over multiple VRAM banks, then you have to set the cycle pattern such that the access of that data is at the same cycles for all banks.
Example:
Assume NBG1 CEL data is in banks A0, A1 and B1 (and NBG1 MAP data in B1).
Correct:
A0: 0x55e....
A1: 0x55e...
B0: 0x55e...
B1: 0x1fe...
Wrong (although it meets all documented restrictions):
A0: 0xe55....
A1: 0x55e...
B0: 0x55e...
B1: 0x1fe...
Correct again:
A0: 0xe55....
A1: 0xe55...
B0: 0xf55...
B1: 0x1ff...
Okay, I think the restriction is weaker and applies only for access in A and B.
Why? Because it sounds so similar to the CPU access restriction, which is:
If you provide CPU access to bank 0 or 1 of A/B, then you'll have to provide CPU access for the other bank (1 or 0) of A/B, too. Meaning A0 and A1 have CPU access at the same cycles, as well as B0 and B1.
Assuming this, the following would be
correct:
A0: 0xe55....
A1: 0xe55...
B0: 0x55e...
B1: 0x1fe...
But that's only my assumption and is untested.
(correct me if I'm wrong)
If some data spans over multiple VRAM banks, then you have to set the cycle pattern such that the access of that data is at the same cycles for all banks.
Example:
Assume NBG1 CEL data is in banks A0, A1 and B1 (and NBG1 MAP data in B1).
Correct:
A0: 0x55e....
A1: 0x55e...
B0: 0x55e...
B1: 0x1fe...
Wrong (although it meets all documented restrictions):
A0: 0xe55....
A1: 0x55e...
B0: 0x55e...
B1: 0x1fe...
Correct again:
A0: 0xe55....
A1: 0xe55...
B0: 0xf55...
B1: 0x1ff...
Okay, I think the restriction is weaker and applies only for access in A and B.
Why? Because it sounds so similar to the CPU access restriction, which is:
If you provide CPU access to bank 0 or 1 of A/B, then you'll have to provide CPU access for the other bank (1 or 0) of A/B, too. Meaning A0 and A1 have CPU access at the same cycles, as well as B0 and B1.
Assuming this, the following would be
correct:
A0: 0xe55....
A1: 0xe55...
B0: 0x55e...
B1: 0x1fe...
But that's only my assumption and is untested.
