antime
Extra Hard Mid Boss
You don't understand the issue. When using an interrupt stack, no task stack space should be used by interrupt handlers. This is not possible on SH2. Even worse, there is an unavoidable small window at the start of every ISR where a higher-priority interrupt can pre-empt the running ISR before the stack pointer can be adjusted. This means the higher-priority interrupt's stack frame will also be pushed onto the user stack, and so on until you reach the highest priority level.
Other architectures solve this by banking some or all of the registers (eg. 68000, ARM) or by automatically disabling interrupts when entering an exception handler (eg. MIPS, SH3/SH4).
Try reading the source in question, maybe you'll figure out what we're talking about.
Other architectures solve this by banking some or all of the registers (eg. 68000, ARM) or by automatically disabling interrupts when entering an exception handler (eg. MIPS, SH3/SH4).
Try reading the source in question, maybe you'll figure out what we're talking about.