vbt
Staff member
SSF Ver0.09 alpha R3
Drive state transition processing of a CD block was corrected.
Timer processing of SCSP was corrected.
RISANPURINGU processing of SCSP was corrected.
DMA end interrupt servicing of SCU was corrected.
Drawing of revolution surface of VDP2 was corrected.
The version of State save data changed.
The main loop processing was changed to the internal system clock center from the master SH2 center.
SH2 Instruction Numbers of an option was changed to 1Block Clock with that.
Maybe it becomes slightly heavy.
HSynch Real Clock option was abolished.
The compilation option was changed from Ver0.09 alpha.
A defect seems to have occurred because of that....
I returned an option to the beginning, so the software to which a defect has gone out from alpha may be corrected.