The EE VU0 and VU1 both are designed to deal with floating point operations; hence being based on a 128kbit instruction length.
Instruction length has essentially nothing to do with what type of math is being used, and VU0/1 have a 32-bit (not kbit) instruction length. I think you mean register width, but even in that case they do have 16 32-bit integer registers, just like SH-4 (and this is ignoring the fact that EE also has a fast MIPS core with its own integer registers and ALU).
The SH-4 (SH7750) has fixed length 16kbit instruction, but can also use 64bit for floating point.
The SuperH instruction set does consist of 16-bit instructions, but the instruction width has nothing to do with the register or ALU width (the EE MIPS core for example has 32-bit instruction length but 128-bit registers)
The SH7750 has also got variable external data paths that can be configured to 8,16,32 or 64bits.
This is a bus interface feature and is transparent to an application programmer. It's for connecting peripherals and memories of different widths and having them all work correctly without having to demangle the words in software. EE doesn't have this problem since it is a custom chip that was designed for PS2.
The MMU in the SH7750 can also be scaled to match cache size.
I have no idea what you mean by this, and I've read Chapter 3 of the SH7750 manual several times.
Also, variable bit depths (16,32,64,128)available to the SH7750 make it more capable of being optimized to deal with tasks that involve the use of smaller intergers.
If you only want a smaller result, you simply ignore the high bits.
What i'm trying to get is the SH-4 is more suited to 2D than the EE and its fixed instruction lengths in VU0 and VU1 which are used as the backbone of the chips number crunching power.
SH-4, VU, and MIPS processors all have fixed-length instructions. And the MIPS core in the EE can take the SH7750 to school in integer ops with both VU procs tied behind its back.
